Charge transport and quantum confinement in MoS2 dual-gated transistors

Fuyou Liao , Hongjuan Wang , Xiaojiao Guo , Zhongxun Guo Ling Tong Antoine RiaudYaochen Sheng Lin Chen Qingqing Sun Peng Zhou David Wei Zhang Yang Chai ,Xiangwei Jiang Yan Liu , and Wenzhong Bao

1State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China

2State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University,Xi'an 710071, China

3Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

4The Hong Kong Polytechnic University Shenzhen Research Institute, Shenzhen 518057, China

5Department of Applied Physics, The Hong Kong Polytechnic University, Hong Kong, China

Abstract: Semiconductive two dimensional (2D) materials have attracted significant research attention due to their rich band structures and promising potential for next-generation electrical devices. In this work, we investigate the MoS2 field-effect transistors (FETs) with a dual-gated (DG) architecture, which consists of symmetrical thickness for back gate (BG) and top gate (TG)dielectric. The thickness-dependent charge transport in our DG-MoS2 device is revealed by a four-terminal electrical measurement which excludes the contact influence, and the TCAD simulation is also applied to explain the experimental data. Our results indicate that the impact of quantum confinement effect plays an important role in the charge transport in the MoS2 channel, as it confines charge carriers in the center of the channel, which reduces the scattering and boosts the mobility compared to the single gating case. Furthermore, temperature-dependent transfer curves reveal that multi-layer MoS2 DG-FET is in the phonon-limited transport regime, while single layer MoS2 shows typical Coulomb impurity limited regime.

Keywords: MoS2; field effect transistors; dual-gate; quantum confinement; Coulomb impurity

1.Introduction

Atomic thick two-dimensional (2D) layered materials,such as semi-metallic graphene and semiconductive transition metal dichalcogenides (TMDCs), have emerged as an attractive candidate for future electronic and optoelectrical materials[1−6]. Among them, molybdenum disulphide (MoS2)is a typical member of TMDCs and considered as a promising candidate for various device applications, mainly due to its prolific, thickness-dependent band structures[7−10]. The singlegated field-effect transistors (SG-FETs) based on MoS2exhibit excellent carrier mobility (～ 200 cm2/(V·s)), high current on/off ratio (> 108), and low subthreshold swing approaching the fundamental thermal limit at room temperature[2].The short channel effects (SCE) can also be suppressed due to the ultra-thin channel body[7,11].

Since the bandgap size is dependent on the MoS2layer number[12−14], bilayer (BL) or multilayer (ML) MoS2tend to achieve higher mobility to carry larger driving current than that of monolayer MoS2. However, the BL or ML-MoS2suffer from the degradation of SS and the current on/off ratio due to weaker channel electrostatic control. To overcome such a problem, the dual-gated (DG) structure, similar to that of Fin-FET technology, provides better electrostatic control over the channel region and is more achievable for 2D-TMDCs[15−18].Liu et al. achieved a back-gate mobility of up to 517 cm2/(V·s)and an on/off ratio higher than 108based on SiO2, Al2O3as the back-gated and top-gated dielectric[19]. Our previously reported results based on a DG-FET with symmetrical back and top gates also indicate that the DG structure is able to modulate the threshold voltage (VTH) and SS by tuning back and top gates separately, and a superior channel current (ID) modulation can be achieved under the DG gating[20−22]. Nevertheless, the charge transport and current distribution influenced by DG structure have not been systematically discussed in TMDCs devices.

Here, we successfully fabricate the MoS2DG-FETs with symmetric back gate (BG) and top gate (TG) based on monolayer and multilayer MoS2films. The thickness-dependent charge transport in our MoS2DG structure is revealed by a four-probe electrical measurement which excludes the contact influence, and TCAD simulation shows that the impact of quantum confinement effect exists in thin MoS2sheet sandwiched by the DG. Such effect attenuates with larger thickness, but still exist in a 5-nm-thick channel. The temperature-dependent electrical measurement of our device also indicates that transport of multilayer MoS2DG-FET is in the phonon-limited transport regime, while single layer MoS2device shows typical Coulomb impurity (CI) limited regime.

Fig. 1. (Color online) (a) Side-view schematic illustration of a MoS2 DG-FET. (b) Optical microscopic image of an exfoliated MoS2 sheet on a 200-nm-thick Al2O3 substrate. (c) Raman spectra of MoS2 sheets with thickness ranging from 1L to 4L. (d) Optical image of a typical 4-terminal device,the top gate electrode is relatively thin (15 nm) but still conductive. The lower graph is a schematic of the 4-terminal device in which W is the channel width and L is the distance between two inner pads. V1 and V2 are used to gauge the voltage drop between two inner contacts.

2.Device structure and material characterization

The cross-sectional schematic of MoS2DG-FET is depicted in Fig. 1(a). The fabrication process for such devices starts from the deposition of a 200-nm-thick Al2O3layer by atom layer deposition (ALD, MNT-100-4) on a heavily doped Si substrate, which acts as a BG dielectric layer. Then multilayer MoS2flakes are mechanically exfoliated on top of Al2O3, and a typical optical microscopic image is shown in Fig. 1(b). Uniform and rectangular shaped MoS2sheets are selected for subsequent device fabrication. Raman characterization (laser excitation wavelength of 514 nm) is then carried out to confirm the layer number and crystalline quality, as shown in Fig. 1(c).To avoid lithography contamination, electrical contacts (5 nm Ti/30 nm Au) are patterned using a stencil mask technique[23].Immediately after the contact deposition, another layer of 200-nm-thick Al2O3is deposited by ALD as TG dielectric, followed by the formation of TG electrodes by traditional photo-lithography, metal evaporation, and lift-off. Electrical transport measurements are performed under an ambient condition with a semiconductor analyzer (Agilent, B1500a).Temperature-dependent measurement was carried out in a cryogenic vacuum probe-station.

The field-effect mobilityμis a crucial factor to characterize the FET performance. For most TMDCs-based FETs, the effective value ofμis mainly governed by the contact rather than the channel itself[24,25]. In order to isolate the intrinsic mobility, we compensate for this effect by utilizing a fourterminal structure to exclude the contact effect. The upper graph of Fig. 1(d) is an optical image of our four-terminal device and the lower graph is a schematic diagram where the two inner voltage probesV1andV2are used to gauge the voltage drop. Then the four-terminal conductivitywhereIDis the channel current andLandWare the length and width of the MoS2channel inside the inner voltage probes, respectively.

3.Experimental result and discussion

The measuredσ4probas functions of BG, TG and DG modes are shown in Fig. 2(a). It is noted that results from BG and TG modes are highly coincident due to their symmetric gating capability, while a weak mismatch at negative gate voltage region can also be observed, which may result from their different dielectric-MoS2interfaces. As for the BG, MoS2is directly transferred on to the pre-deposited Al2O3, while for the TG, the interface quality degrades because of the absence of dangling bonds on MoS2for deposition of Al2O3.

It also shows that DG mode displays an improved channel electrostatic control than that of BG or TG. To further illustrate the gate modulation by BG and TG, a 2D contour plot ofσ4probas functions ofVBGandVTGis then plotted in Fig. 2(b).Such 2D diagram shows parallel diagonal contours with constant current, and the slope of these contours line is approximately 1, indicating that the BG and TG exhibit the same capability to modulate the channel, since the oxidation layer capacitance of the back gate and top gate is nearly symmetrical(CBG/CTG≈ 1).

Fig. 2. (Color online) (a) Four-terminal conductivity σ4prob as functions of BG, TG and DG voltages. Solid and dashed curves correspond to linear and logarithmic coordinates, respectively. (b) 2D contour plot of σ4prob as functions of VBG and VTG at room temperature. (c) Mobility versus sheet thickness collected from 10 MoS2 DG-FETs work under DG mode.

For SG structure, the field-effect (FE) mobility can be estimated byunit are a (40 nF/cm2for 200 nm of Al2O3),VGis the gate voltage, andeis the elementary charge. While in the case of a symmetric DG structure and considering top and bottom surfaces of MoS2as parallel channels, we can estimate that the total conductivityσ’DG=σBG+σTG. SinceC’ox-DG≈ 2Cox,we expect that the quantityμ’DG= (μBG+μTG)/2 will be equal toμDGestimated by theσDG–VDGcurve. However, it appears that directly measuredμDGis generally larger thanμ’DG,which indicates the inadequacy of this parallel channel model. We then use ΔμDG= (μDG–μ’DG)/μ’DGto quantify the mobility enhancement of dual gating, and plot in Fig. 2(c) ΔμDGandμDGas functions of the channel thickness. It is noted that both device mobility and ΔμDGreach a maximum with the MoS2thickness in the range of 2–6 nm, and such thickness-dependentμDGdeviates from previously reported results with only BG[24,26,27], indicating a different carrier transport mechanism in our DG-FETs.

Fig. 3. (Color online) (a) With and (b) without considering quantum confinement effect, the simulation results of carrier redistribution of a 2-nm-thick MoS2. The upper and lower panels show the simulation results from the SG (VBG = 10 V) and DG (VBG = VTG = 10 V) device, respectively. (c) The electron density in the channel of the DG MoS2 device versus channel thickness. The dielectric layer is 200 nm Al2O3. for all devices

Depending on the channel thickness, there is a competition of multiple mechanisms in our MoS2DG-FETs: 1) larger current carrying ability in thicker channels, but with considerable interlayer resistance[24]; 2) current redistribution due to the DG induced quantum confinement effect; 3) electrical transport exposed to extrinsic Coulomb scattering from highkdielectrics (e.g. Al2O3, HfO2) and interface for ultra-thin channels. Therefore, the experimental results exhibit their overall competitional effects. While the first and the third factors may have a negative effect on the mobility, we now focus on the quantum confinement effect, which may avoid the interfacial scattering and enhance the carrier mobility.

Fig. 4. (Color online) Temperature dependence electrical measurement. (a) The temperature-dependent σ as a function of VDG of a four-probe device. MoS2 is ～5 nm thick with 200 nm Al2O3 of both TG and BG dielectrics. (b) The temperature-dependent mobility extracted from monolayer MoS2 (black dot) and multi-layer MoS2 DG-FET (red square). Monolayer MoS2 DG-FET is 15 nm HfO2 of both TG and BG dielectrics.

To ravel the impact from quantum confinement effect,the carrier density, and distribution of the DG-FETs are then simulated by using the van Dort model, the 1D Schrödinger equation, the density gradient model, and the modified localdensity approximation (MLDA). The van Dort model computes the impact of electric field normal to the channel interface on the carrier density modification due to the quantization. Based on the energy band structures in the channel, the 1D Schrödinger equation was solved self-consistently with the Poisson equation. The eigenvalues and wave functions for electrons and holes were obtained with consideration of multi valleys in conduction and valence bands. The density gradient model added the quantum correction to the carrier distribution at interfaces in the device by introducing the reciprocal thermal energy, mass-driving term, and the smoothed potential[28]. In this model, the bandgap narrowing effect and apparent band-edge shifts caused by multistate configurations were involved. The MLDA model calculates the distribution of confined carriers near the dielectric/channel interface. In our simulation, the multi valley properties of conduction and valence bands were considered in MLDA model.

Figs. 3(a) and 3(b) compare the quantum-confinement impact on the simulated carrier redistribution in SG (VBG= 10 V)and DG (VBG=VTG= 10 V) structures. In the DG structure,quantum confinement effect is rather prominent, it repulses carriers away from dielectric-MoS2interfaces and confines carriers inside the channel, which can suppress phonon and Coulomb scattering at interfaces and contribute to the mobility improvement. On the opposite, the carriers in the SG structure are pushed towards one side of MoS2, amplifying the interface scattering. Fig. 3(c) shows the calculated carrier distribution in MoS2DG device with a series of channel thicknesses,by considering quantum confinement effect. It is noticed that the impact of quantum confinement effect attenuates with larger thickness but still exist in a 5 nm thick channel.

Thus, a complete scenario for thickness dependence of MoS2DG-FET can be: thicker MoS2carries current larger but with less quantum confinement effect, and there are also trade-offs including large interlayer resistance and screening effect than weakens the gate control. For practical applications of MoS2FETs, considering critical parameters includingμ, SS and current on/off ratio, a layer thickness in the range of 2–6 nm would be ideal by achieving overall satisfyingμ, SS and current on/off ratio[21], which is competitive comparing to best SOI[29].

We then investigate the temperature-dependent electrical properties of our MoS2DG-FETs. Fig. 4(a) shows the temperature-dependent transfer curve from a multilayer MoS2device (～ 5 nm). The channel current increases when temperature decreases, while the threshold voltageVTHhardly shifts when lowering the temperature. In the 4-terminal device architecture, mobility extraction is more accurate, as shown in Fig. 4(b). The mobility in a multi-layer MoS2DG-FET is as high as 763 cm2/(V·s) (n≈ 1013cm–2) at 125 K (plotted by red point) and can be fitted byT–γforT> 100 K withγ= 2.5,which is in good agreement with theoretically predicted value (γbetween 1.52 and 2.6)[30,31]. This indicates that our multilayer MoS2DG-FET is in the phonon-limited transport regime. While the temperature-dependent mobility of a monolayer MoS2device (grey points) shows typical CI limited regime, especially at low temperature. The CI limited mobility(μCI) can be well fitted by our calculation (plotted by gray dash) considering screening effect by surrounding dielectrics[32,33](15-nm-thick HfO2for this device) withn≈ 1013cm–2and impurity densityNl≈ 2 × 1013cm–2. Such difference can also originate from the quantum confinement effect but a more detailed investigation is necessary to achieve an indepth understanding in the future.

4.Conclusion

We reported a systematic investigation of carrier transport in MoS2DG-FETs with a variation of MoS2channel thickness. DG structure provides better electrostatic control for the MoS2FETs. Moreover, quantum confinement plays an important role in the charge transport, as for a certain thickness of MoS2, confinement of the charge in the center of the channel under DG mode reduces the scattering and thus boosts the mobility compared to single gating of a similar thickness layer. The TCAD simulation considering quantum confinement reveals that the impact of quantum confinement effect attenuates with larger thickness but still exist in a 5 nm thick channel. Furthermore, the phonon-limited transport regime and CI limited regime were revealed in multi-layer MoS2DG-FETs and single layer MoS2by temperature-dependent transfer curves, respectively. Such device architecture together with similar results can be extended to other TMDCs based devices.

Acknowledgements

This work was supported by the National Key Research and Development Program of China (2016YFA0203900,2018YFA0306101), the National Natural Science Foundation of China (Grant No. 91964202), and Shanghai Municipal Science and Technology Commission (18JC1410300).